The present invention relates to integrated circuits, and more particularly to switching voltage regulators formed in an integrated circuit.
Voltage regulators are often used to generate a lower DC voltage from a higher, unstable DC supply voltage. One type of voltage regulator, commonly referred to as a switching voltage regulator, typically includes a switching element, such as a transistor, and an inductor disposed between the voltage source and an output load. The switching regulator regulates the voltage across the load by turning the switching element on and off, thereby enabling current pulses to be delivered from the voltage source to the inductor. The inductor together with a capacitor convert the current pulses to a substantially constant load current so as to regulate the load voltage.
FIG. 1 is a schematic diagram of a current-mode step-down switching regulator 100, as known in the prior art. To increase the output voltage VOUT, current is supplied to inductor 118 by closing switch 128 and opening switch 126. To decrease the output voltage VOUT, current is withdrawn from inductor 118 by closing switch 126 and opening switch 128. Switches 126 and 128 are opened and closed in response to control signals C1 and C2 generated by control logic 110.
Feedback voltage VFB generated using resistors 122 and 124 is fed back to the negative input terminal of amplifier 102. Amplifier 102 may be a transconductance amplifier and is alternatively referred to below as an error amplifier. Amplifier 102 is adapted to generate a signal VITH that is proportional to a difference between voltage VFB and a reference VRef. Reference voltage VRef may be supplied by a bandgap circuit and is adapted so as not to vary substantially with supply voltage, temperature, etc. Compensation circuit 142 is coupled to the output terminal of amplifier 102 when switch 140—shown as being responsive to signal Sleep—is closed. Compensation circuit 142 stabilizes amplifier 102 against a number of factors, such as supply voltage variations, temperature changes, etc, as is well known in the art.
Hysteretic comparator 104 is adapted to compare signal VITH with reference voltage VB1. If voltage VITH is detected as being higher than an upper level of a voltage band defined by reference voltage VB1, output voltage Sleep of comparator 104 switches to a high state. If, on the other hand, voltage VITH is detected as being smaller than a lower level of the voltage band defined by reference voltage VB1, output voltage Sleep of comparator 104 switches to a low level. When signal Sleep is asserted, e.g., is at a high level, compensation circuit 142 is decoupled from amplifier 102, voltage limiter 106 is shut down, signal C1 causes switch 128 to go into a high-impedance mode, and signal C2 causes switch 126 to go into high-impedance mode when the switch current approaches zero, thus placing voltage regulator 100 in a standby mode so as to reduce the quiescent current. When output voltage VOUT starts to fall below a certain value, comparator 104 switches again, thereby causing signal Sleep to be de-asserted to resume normal operation.
Voltage limiter 106 compares voltage signal VITH with another reference voltage VB2. If voltage signal VITH is detected as being greater than voltage level VB2, voltage limiter 106 delivers output voltage signal VITH at its output terminal unchanged. If signal VITH is detected as being smaller than voltage level VB2, voltage limiter 106 clamps signal VITH to voltage level VB2 and delivers the voltage level VB2 at its output terminal. In other words, voltage limiter 106 ensures that its output voltage Vclamp does not fall below voltage level VB2.
Current I1 causes a voltage V1 to develop across resistor 116 disposed across the input terminals of comparator 108. Voltage Vclamp varies the trip point of comparator 108. If voltage V1 is detected as being smaller than voltage Vclamp, output signal B of comparator 108 is maintained at a first state, e.g. a low logic state. Conversely if voltage V1 is detected as being greater than voltage Vclamp, output signal B of comparator 108 is maintained at a second logic state, e.g. a high logic state.
Control logic 110 receives signals Sleep and B, and in response generates control signals C1 and C2. If signal B is at, e.g., a low logic level, signals C1 and C2 are respectively caused to be at high and low levels, thereby causing switch 128 to be on and switch 126 to off. In other words, if voltage V1 is detected as being smaller than voltage Vclamp, switch 128 is turned on and switch 126 is turned off. Accordingly, current I1 is enabled to flow to inductor 118 and resistor 122 to thereby raise output voltage Vout.
Conversely, if signal B is at, e.g., a high logic level, signals C1 and C2 are respectively caused to be at low and high levels, thereby causing switch 128 to turn off and switch 126 to turn on. In other words, if voltage V1 is detected as being greater than voltage Vclamp, switch 128 is turned off and switch 126 is turned on. Accordingly, current I2 is withdrawn from inductor 118 and resistor 122 to thereby decrease output voltage Vout.
Switch regulator 110 is also shown as including comparators 112 and 114, as well oscillator 130. Comparator 112 is adapted to assert its output signal Vunder if comparator 112 detects that feedback voltage VFB is smaller than voltage Vref−ΔV. Comparator 114 is adapted to assert its output signal Vover if comparator 114 detects that feedback voltage VFB is greater than voltage Vref+ΔV , where ΔV is a predefined voltage level. Oscillator 130 supplies a clock signal to control logic 110.
The amount of ripple appearing at output voltage VOUT is determined, in part, by the difference between the trip points of comparator 104 divided by the gain of amplifier 102. Therefore, to decrease such ripples, the difference between the trip points of comparator 104 is required to be reduced and/or the gain of amplifier 102 is required to increase. As is well known, the gain of amplifier 102 is dependent, in part, on the electrical characteristics of the components disposed in compensation block 142. While compensation circuit 142 stabilizes amplifier 102 it also loads the negative input terminal of comparator 104. This loading causes comparator 104 to be relatively slow and unable to follow the variation in output signal VOUT, in turn, causing ripples to appear on signal VOUT.
To reduce the output voltage ripple, amplifier 102 and comparator 104 may be coupled in parallel, as shown in switching voltage regulator 200, displayed in FIG. 2. Because in embodiment 200, comparator 104 is not loaded with the compensation circuit 142, output ripple voltage is reduced. However, the difference between the offset voltages of amplifier 102 and comparator 104 causes a number of disadvantages. It would thus be desirable to have a switching voltage regulator that has a reduced output ripple voltage and that overcomes the problems described above.